Capacitively coupled logic gate

ABSTRACT

An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.

RELATED APPLICATIONS

The present application is a continuation of U.S. patent applicationSer. No. 13/233,767, filed Sep. 15, 2011, which claims the benefit under35 U.S.C. 119(e) of the priority date of Provisional Application Ser.No. 61/383,128 filed Sep. 15, 2010. Both of those applications arehereby incorporated by reference in their entireties.

FIELD OF THE INVENTION

The present disclosure pertains to semiconductor logic gates,particularly those which can be implemented using capacitive coupling.

BACKGROUND

Reference is made to U.S. Pat. Nos. 7,782,668 and 7,787,295 and U.S.patent application Ser. Nos. 12/264,029, 12/264,060, 12/264,076,12/271,647, 12,271,666 and 12/271,680 all of which are herebyincorporated by reference.

The '668 patent discloses a new type of single-poly non-volatile memorydevice structure that can be operated either as an OTP (one timeprogrammable) or as an MTP (multiple time programmable) memory cell. Thedevice is programmed using hot electron injection. It also has astructure that is fully compatible with advanced CMOS logic process, andwould require, at the worst case, very minimal additional steps toimplement. Other unique aspects of the device are described in the '668patent as well.

SUMMARY OF INVENTION

An object of the present invention is to extend the use of capacitivecoupling to specific types of logic devices and circuits.

In accordance with this object a plurality of areal capacitive couplingdevices are coupled to process a set of data inputs; each is preferablyconfigured such that a floating gate potential of such device can bealtered in response to receiving an input signal from the set of datainputs; the floating gate potential can be adjusted to place the arealcapacitive coupling device into a first state or a second state throughareal capacitive coupling to a potential associated with a first activeregion receiving the input signal; the areal capacitive coupling devicesas interconnected generate a first logic output which is a first logicalfunction associated with the set of data inputs.

Other objects of the invention include methods of operating a dualfunction gate in which the device performs a different circuit functiondepending on a level is of an input signal applied to such logic gate;

Another object is to provide a logic gate with N inputs and in which aselected set M of inputs (M<=N−2) can be considered for purposes ofdetermining a logical majority function.

A further object is to provide an electronic circuit in which logicgates can also be imbued with a memory function to allow for dualfunctionality.

DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a preferred embodiment of a circuit implementing a3-input majority function.

FIG. 2 depicts the Load Line characteristics of the 3-Input CapacitiveCoupling Device and Pull Down transistor shown in FIG. 1.

DETAILED DESCRIPTION

Applicant has discovered that the '668 gate/drain overlap device usingareal capacitive coupling (hereinafter referred to as the “capacitivecoupling device”) can be used in non-memory applications as well. Asdiscussed herein, the device's unique characteristics can be used toefficiently implement a number of CMOS logic functions, including,preferably, one of the most device consuming and yet useful—the MajorityFunction.

FIG. 1 below illustrates a preferred implementation of a 3-inputmajority function logic gate 100 implemented with three (3) '668capacitive coupling devices (shown at the top of the figure as 10A, 10Band 10C) along with standard CMOS transistors (including a pair ofinverters on the right —20A/20B, and a conventional N MOS pulldown FET30) at the bottom). It will be understood by those skilled in the artthat other combinations and connections of devices could is be used toeffectuate the same result of the exemplary gate shown in FIG. 1,including of course for larger numbers of inputs.

The output voltage characteristics, with the capacitive coupling devicesas load lines, of the above 3 input circuit is illustrated in FIG. 2. Ascan be seen from the figure, if 2 or more (a majority) of the inputs todevices 10A/10B/10C are conducting, the intersecting point will yield anoutput voltage that is higher than the VIH of the inverter circuit(20A/20B), and will allow the output of the voltage after the twoinverter stage to be high, fulfilling a majority function.

Conversely, if only one or none of the inputs (not majority) isconducting, the output voltage is below VIL, and will not be able totrigger the inverter. This is how a 3-input majority function ispreferably implemented; namely with 3 capacitive coupling devices, 1pull-down transistor, and 2 pair of NMOS and PMOS transistors for 2inverter circuits. All of these devices are conventional, and to ensureadequate margin of operation it is preferable to perform simulations toselect and match the size of the various transistors. This can beaccomplished using any number of well-known design tools, and iscommonly done in providing logic cell libraries, so it is well withinthe skill of the ordinary artisan without undue experimentation.

The transistor count saving, and the subsequent silicon area saving,become geometrically larger when the number of inputs for the majorityfunction increases. For example, for a 5-input majority function, only 5capacitive coupling devices, 1 matched pull-down transistor, and 2 pairof NMOS and PMOS transistors for 2-stage inverter circuit are required.In general, for any N input majority function gate, the device countwill be N capacitive coupling devices and an additional set of 5 supporttransistors.

One reason that using the capacitive coupling device implementation of alogic gate is advantageous is that a conventional N-channel floatinggate device would not be able to turn on if the drain coupling is nothigh enough to overcome the Vt of the NMOS device. The present devicehas a high coupling ratio to allow sufficient voltage coupled to thefloating gate to turn on the device in accordance with a target/nominalVt implant process used in the IC manufacturing flow.

Persons skilled in the art will appreciate from the present teachingsthat the majority function can be implemented in an alternativeembodiment in which the invention is taken to an extreme and 100%coupling is used, i.e., such as to effectuate a form of NMOS gated diode(e.g., NMOS with gate connected to the drain directly). The disadvantageof this approach is that it removes one degree of process freedom, inthat the only remaining mechanism to control the switching/output of thedevice is through adjusting the nominal Vt for the device, a tradeoffthat may result in compatability problems with the CMOS parameters ofother devices in the integrated circuit, as well as complicate thematching of the logic circuit output to the pulldown FETcharacteristics.

A capacitive coupling device implementation with less than 100% couplingoffers an advantage over a pure NMOS gated diode implementation, sincethe output current of the capacitive coupling device can be tailoredspecifically through the coupling capacitance, without altering thebaseline CMOS process parameters (such as Vt) used by other logiccircuits, and allowing the logic function to be implemented optimally toother related circuit elements, such as the pulldown FET. Thus thepresent invention affords a more flexible technique to implement a logicfunction since a nominal logic gate Vt and related process parameterscan be used as a driver to determine sizings of the gates/activeregions, and the extent of the coupling ratio (∀) that should be usedfor any particular circuit.

Other variants of the invention can include hardwired logic (i.e., aPLD, programmable logic) and conventional CMOS logic functions, albeitmore efficient in device counts. By allowing embedding of the devicewithin a CMOS process, one can implement a “hardwired” look-up table toimplement some logic function, much like an FPGA.

Another advantage of using the preferred embodiment of this invention isthat the situation where an input to the majority function may no longerbe valid can be addressed with the use of capacitive coupled devices asdescribed in '668. If an input is no longer needed, the associatedcapacitive coupled device is can be programmed to be off and be removedfrom being considered in the output of the logic function. That is, anyone or more of the logic devices in the circuit can be configuredeffectively by a function select signal. The function select signal canapply a potential to the logic device so that it instead behaves as aquasi-memory device. That is, the device behaves effectively like amemory gate, not a logic gate, when the floating gate is raised to asufficiently high potential. This has the effect of turning the deviceoff (i.e., rendering it non-conductive) and thus selectively enabling ordisabling its participation in a circuit logic function. In someembodiments the output or function can be hardwired or burned in duringmanufacturing. This can be accomplished by predetermined programmingrespective inputs to the logic gates, to configure them into an erasedor programmed state as desired.

Other variations of circuits of the capacitive coupled dual functiondevices can be employed of course, and the invention is not limited inthis respect. Many types of conventional circuits are expected tobenefit from devices which can adjust their behavior dynamically inresponse to a function select signal.

Thus certain embodiments of the present invention can be implemented sothat a majority function circuit can be altered to render a majorityfunction for any subset of the inputs. For example, even with maximum of5 inputs, one can still program the circuit to be a majority function ofany of the 3 inputs. With a set of 7 inputs one can consider the stateof a selected subset of 5 inputs, and so on. Other variations will beapparent to those skilled in the art.

This advantageous feature could potentially offer a significant savingin the circuit design since costly revision of the silicon design andits associated process cost can be avoided.

While this preferred example illustrates a majority function logic gate,those skilled in the art will appreciate from the foregoing that this isjust an example and that other complex CMOS logic gates can beimplemented using the capacitive coupling devices as well. It isexpected that the novel capacitive coupling device can be utilized in anumber of applications in a non-memory is capacity as a substitute for aconventional FET.

What is claimed is:
 1. An electronic logic circuit comprising: aplurality of two terminal areal capacitive coupling gates coupled toprocess a set of data inputs; each two terminal areal capacitivecoupling gate being a single gate configured such that a voltagepotential of a floating gate of such single gate can be altered inresponse to receiving a single input signal from said set of datainputs, said floating gate being configured to place said two terminalareal capacitive coupling gate into a first state or a second statethrough areal capacitive coupling to a potential associated with a firstactive region of such gate receiving said single input signal; each twoterminal areal capacitive coupling gate further being configured by afunction select signal to be on or off so as to enable the electroniclogic circuit to process and implement a majority function operationwith a selected subset of two terminal areal capacitive coupling gatesfor a selected subset of is said set of data inputs; an output of eachof said selected subset of two terminal areal capacitive coupling gatesbeing related to said first state or said second state, such that aplurality of separate selected outputs can be generated by said selectedsubset of two terminal areal capacitive gates; and an output of each twoterminal areal capacitive coupling gate of said selected subset of twoterminal areal capacitive coupling gates being related to said firststate or said second state, and said selected subset of interconnectedtwo terminal areas capacitive gates being configured to generate aplurality of separate outputs from a plurality of separate ones of saidset of data inputs; wherein said plurality of separate outputs of saidplurality of interconnected two terminal areal capacitive coupling gatesprocess separate single ones of said set of data inputs and effectuate acollective output corresponding to a logic function implemented for saidselected subset set of data inputs.
 2. The logic circuit of claim 1,wherein said logic function is a majority gate function implemented on alimited variable number of a maximum number of inputs to said logiccircuit.
 3. The logic circuit of claim 1, wherein said two terminalareal capacitive coupling gates operate using channel hot electroninjection.
 4. The logic circuit of claim 1, wherein said function selectsignal is hardwired by an electrical connection to an interconnect mask.5. A method of operating a logic circuit using a dual functionelectronic logic gate which is a single gate that employs arealcapacitive coupling between a source/drain region and a floating gatecomprising: a. enabling the single gate to perform a first circuitfunction within the is logic circuit when a first selection voltage isapplied to an input terminal of the device coupled to said source/drainregion; b. enabling the single gate to perform a second circuit functionwithin the logic circuit when a second selection voltage is applied tosaid input terminal; wherein the first circuit function is a memoryfunction, and second circuit function is a switching function; whereinthe dual function electronic logic gate only participates in a logicfunction implemented by the logic circuit when configured to performsaid first circuit function; and further wherein the first input voltageeffectuating a memory function for the dual function electronic logicgate is substantially higher than said second input voltage effectuatingsaid switching function.
 6. The method of claim 5, wherein said stepsare performed for multiple dual function electronic logic gates in thelogic circuit.
 7. The method of claim 6, wherein only a subset ofavailable dual function electronic logic gates are configured with saidfirst circuit function.
 8. The method of claim 5, wherein said firstselection voltage is at least 2× said second selection voltage.
 9. Themethod of claim 5, wherein said first selection voltage is sufficientlyhigh to cause hot electron injection onto the floating gate of the dualfunction electronic logic gate.
 10. The method of claim 5, wherein saidinput terminal is electrically connected by an interconnect mask to onlyone of said first selection voltage or second selection voltage.